Almost all new IoT/edge devices that can run Linux use either the x86 architecture (mostly Intel, some AMD) or Arm, which is licensed by vendors like Qualcomm, Nvidia, NXP, Huawei, and Samsung. Arm is ubiquitous in smartphones and dominant among open-spec, community-backed SBCs such as the Raspberry Pi (see What is an SBC?). When referring to such boards, I prefer to use the term open-spec. Even if a project is scrupulous in meeting open source requirements, there is always at least one component that is proprietary: the processor.
RISC-V Advances: IoT, Datacenter, and Cloud
The open RISC-V architecture is beginning to change that. It has been five years since RISC-V emerged from UC Berkeley, where it was developed in part by David Patterson, a principal creator of the RISC architecture used by Arm (Advanced RISC Machine). RISC-V International members include most of the major tech companies and chip manufacturers. These include Arm licensees such as Nvidia, which is acquiring Arm. Many have incorporated RISC-V based components in proprietary processors, and a few have launched RISC-V CPUs.
RISC-V represents only a tiny share of the chip market, but it is growing fast. The early growth was in microcontrollers; over the past year, we have seen more IoT chips that can run Linux. As a sign of RISC-V’s rapid advance, in May RISC-V International announced it was giving away 1,000 free RISC-V development boards, some of which run Linux.
Neither is the datacenter immune to the RISC-V onslaught. A March report from DataCenter Knowledge says that RISC-V is being used in datacenter accelerator chips, and that “some HPC networks use RISC-V to process data in transit.” The story adds that Alibaba and others have begun to deploy RISC-V as CPUs in cloud servers. In another HPC-focused project, the 28-member, 10-country European Processor Initiative (EPI) recently announced it has taped out a Linux-ready EPAC 1.0 core.
Intel recently announced a new Intel Foundry Services to fabricate chips for startups, including designs based on RISC-V IP from leading RISC-V core vendor SiFive. Since RISC-V will initially challenge Arm more than Intel, the gesture is relatively “risk” free.
RISC-V Advantages: Cost, Customization, and Modernity
RISC-V appeals on many levels, starting with free licensing of the base instruction set. Some companies are releasing open source CPU core IP, and costs for licensed core IP, which tend to include access to EDA tools, simulators, emulators, support, and more, tend to be much lower than Arm’s terms.
The prospect of avoiding high licensing fees is particularly appealing to smaller firms creating custom AI chips with relatively small runs. Such customized chips are growing in popularity due in part to the degradation of Moore’s Law — by optimizing for a particular task, chipmakers can improve effective performance without dramatic process enhancements. Another factor is the proliferating use cases for IoT and edge AI systems, as explored in our three-part Internet of Things series.
The advantages of customization and reuse are equally appealing. If a chipmaker has full control of its chip design and can re-use and borrow code, it can more easily customize chips for different applications.
Most RISC-V developers share at least some of their code, which encourages reuse and reduces development time. Yet, RISC-V offers a permissive license that permits chipmakers to use RISC-V to create proprietary designs. The option to go proprietary with all or part of the design is appealing to many manufacturers. To keep proprietary RISC-V development in check, RISC-V International grants a trademark to projects that follow RISC-V’s guidelines for openness, flexibility, and modular extensions.
EETimes quotes SiFive co-founder Krste Asanovic, speaking at CES 2021, as saying: “RISC-V isn’t an open source processor. Instead, it’s an open standard for developing a processor.”
Chipmakers also appreciate the competitive advantage of not being forced to publicize their use of RISC-V, as required by Arm. As a result, there is likely more RISC-V development going on than is evident. On the other hand, most chipmakers proudly announce their RISC-V projects to demonstrate they are hip to the latest trends and to “virtue signal” their open source bona fides.
Aside from cost and customizability, RISC-V benefits from being a modern, elegantly designed architecture without the baggage of legacy code found on Arm, x86, PowerPC, and MIPS. Along with the open development environment, the modern design appeals to developers, who are increasingly crucial to success. Earlier this year, MIPS Technologies, which had previously open sourced some chip designs with little uptake, joined RISC-V International and is now working on a new version of MIPS that switches to RISC-V.
Although RISC-V chips have yet to match the processing power of high-end Arm designs, let alone Intel and AMD chips, there is nothing inherent in the architecture that could stop it from catching up. Meanwhile, RISC-V appears to enable greater power efficiency. In December, Micro Magic unveiled a RISC-V core shown to offer a groundbreaking 110,000 CoreMarks/Watt, with a 3GHz chip consuming less than 70mW.
On the other hand, RISC-V has yet to move much beyond CPUs and MCUs, with GPUs being the biggest omission. As a result, most Linux-ready silicon is designed for headless applications. Yet earlier this year, a project emerged to build a RISC-V GPU based on RISC-V’s new RV64 vector extensions, which can also be used for AI acceleration. Commercial implementations are expected by 2024.
Independent and International
RISC-V’s independence from single companies or countries — reinforced by the recent re-launch of RISC-V International in Switzerland — plays well in this age of nationalism and trade wars. A recent IEEE Spectrum survey report noted that while RISC-V membership is about equally divided between North America, Europe, and Asia, the latter is seeing the fastest adoption in recent years, with China leading the way.
RISC-V adoption is expected to increase once US-based Nvidia acquires Arm, with Chinese firms in particular concerned that all the major chipmaking platforms will be headquartered in the US. Huawei recently revealed a RISC-V based HiSilicon Hi3861 processor that runs its new Android-inspired HarmonyOS.
Even US Arm licensees are wary of the potential loss of Arm’s independence under Nvidia. US nationalists may see RISC-V as a threat to the country’s tech dominance, but that is not likely to stop US tech companies from joining the party.
Arm has responded to the RISC-V threat by offering Custom Instructions extensions, Arm Flexible Access licensing, and a customizable, Armv9 Cortex-X2 core. Yet the licensing is still proprietary, with limited customization available to all but the largest chipmakers.
Recent Linux on RISC-V Highlights
Linux-ready RISC-V processors are coming on fast. Here is a quick roundup of major players and developments:
SiFive — Silicon Valley based SiFive, which is staffed by some of the founders of RISC-V, has led early development in core IP and silicon, both in microcontrollers and higher-end Linux chips. Last fall, SiFive announced a 64-bit, Cortex-A55 like FU740 SoC and launched its second Linux-driven dev kit based on the penta-core FU740 called the HiFive Unmatched. SiFive recently announced a SiFive Intelligence X280 core with AI capabilities enabled via RISC-V’s new RV64X vector extensions. We can soon expect to see a Cortex-A72-like U8-Series.
SiFive cores are also being used by other chipmakers. Microchip, which has been a major RISC-V player in MCUs, combined SiFive’s earlier FU540 cores with its own PolarFire FPGA in its Linux-ready PolarFire SoC, which is available on a PolarFire SoC Icicle Kit. Earlier this year, BeagleBoard.org and Seeed announced a BeagleV SBC-based on StarFive’s JH7100 SoC which offers dual SiFive U74 RISC-V cores, a 1-TOPS NPU, a DSP, and a VPU. Antmicro recently announced an ARVSOM module based on a similar StarFive 71x0 variant.
Alibaba/Allwinner — After announcing the Linux-ready XuanTie 910, the first 16-core RISC-V SoC, Alibaba teamed up with Allwinner to launch a Linux-ready, single-core Allwinner D1 SoC. The D1 is available on Sipeed’s $99 Nezha SBC. Sipeed will soon follow up with a D1-based board that will cost under $13. Pine64 is also working on a D1-based SBC.
Andes, Codasip, and Western Digital — Andes has developed Linux-ready A45, A27, and A25 core IP designed for single-core SoCs and is following up with a NX27V variant that supports the same RV64X extensions adopted by SiFive and Alibaba/Allwinner. Last December, Codasip announced three Linux-friendly, 64-bit RISC-V cores: an edge AI oriented A70XP and up to quad-core A70X MP and A70XP MP models.
Another major player in RISC-V is Western Digital, which offers some 32-bit SweRV cores for storage controllers that are equivalent to Cortex-A15. The company has contributed the open source core to the Linux Foundation’s CHIPS Alliance, which is curating and developing RISC-V software.
RISC-V is not immune to the current chip shortage, which will result in delays of silicon launches. Yet, the same does not apply to software. The work of designing and improving cores, enhancing support for Linux and other OSes, and writing all the other code for RISC-V security, verification, and more is accelerating. When the chip pipeline starts moving again, RISC-V will be ready to roll.
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